September 26, 2023 – Investorideas.com (www.investorideas.com), a global investor news source covering tech stocks releases a special news report on how AI is the future evolution of Electronic Design Automation (EDA) tools, featuring a tech innovator building a growing IP portfolio in the sector, GBT Technologies Inc. (OTC PINK:GTCH).
According to allaboutcircuits.com,”For years, EDA companies have claimed “artificial intelligence” features in their IC design tools. In the past year, however, generative AI has undergone a dramatic evolution with platforms like ChatGPT, causing some designers to question whether previous EDA features still count as AI by today’s standards.”
So what is the new standard for AI in EDA?
GBT Technologies Inc. (OTC PINK:GTCH) CTO, Danny Rittman, discussing the issue told Investor Ideas, “Indeed the dominant EDA companies like Synopsis, Cadence, Siemens invested lots into AI in the past decade, yet, the solutions that they provide are not sufficient as the industry struggles to design microchips in an affordable time frames. Projects are delayed, taking way longer than planned and there is a real need for an AI breakthrough.”
Rittman recently published a paper on the topic titled, ‘A Qualitative Study that Explores the Implementation of Artificial Intelligence in Integrated Circuit Design’ https://www.proquest.com/docview/2860456194
Excerpt: “Reports of the early stages of IC chips designed by artificially intelligent aided by deep
neural network learning have appeared recently (Dinu & Ogrutan, 2019). Over the last decade,
there has been significant growth in the integration of AI technologies within Electronic Design
Automation (EDA) tools. AI has played a pivotal role in enhancing various aspects of EDA, such
as design automation, optimization, verification, and physical design (Todorov & Dabral, 2020).
Typical AI techniques used in the EDA field include machine learning (ML), deep learning,
genetic algorithms, natural language processing (NLP), and reinforcement learning.”
Regarding its EDA technology, GBT Technologies Inc. (OTC PINK:GTCH) recently announced it has received a grant notification for its microchip’s reliability verification and auto-correction EDA patent application, internal project’s code name, Epsilon. The patent will be granted as U.S. Patent No. 11,763,062 on September 19, 2023. GBT’s Epsilon patent application covers the innovative technology to address advanced semiconductor node physics with the goal of ensuring a high level of reliability, optimal thermal design, lower power consumption and high performance.
The described technology includes machine learning algorithms to enable robust design, process optimization, characterization, modeling, and simulation. The technology underlying the patent identifies reliability flaws, describes the found issues, and allows an automatic correction of these reliability issues early during the IC’s design phase. Machine Learning techniques will be performing data analysis, identification, categorization, and reasoning about executing the optimal IC layout automatic correction. The technology aims to allow IC designers to analyze and fix circuits early during the design phase in real time with the goal of creating higher efficiencies. GBT plans to continue its R&D efforts in this domain, inventing modern technologies and enabling reliable, low-power, high-performance, next-generation microchips.
“We are excited to share that our Epsilon patent has been granted. This patent aims to perform an early electrical and power analysis of a microchip during the design phase. The goal is to identify potential failures and provide solutions as early detection and elimination of reliability issues can save a significant amount of time in engineering redesign. The technology is planned to be powered by GBT’s machine learning algorithms for pattern recognition and vast data analysis, especially for advanced manufacturing nodes like 3nm and below.
“Today’s advanced nanometer nodes require analysis and addressing of reliability parameters to mitigate risks of system degradation, overheating and possible malfunctions. As IC’s manufacturing nodes are constantly scaling down, layout electrical characteristics analysis is becoming a much more complex and time-consuming process, addressing challenging physics phenomenon.
Our Epsilon patent is an intelligent design productivity enhancement EDA software solution that analyzes, detects, and eliminates electrical reliability issues on-the-fly. Its goal is to enable chip designers to keep their hands on the pulse of the entire microchip’s reliability, power management, thermal behavior and overall performance.
“Microchip reliability is a complex and evolving field. As such, we plan to continue our ongoing research and development efforts to address emerging challenges associated with shrinking nanometer-scale technologies. Additionally, we plan to file a continuation for this technology, with the goal of further broadening and protecting our intellectual “property” stated Danny Rittman, the Company’s CTO.
Synopsys (Nasdaq:SNPS), a global leader in electronic design automation (EDA) and semiconductor IP announced earlier this month, the extension of its Synopsys.ai™ full-stack EDA suite with a comprehensive AI-driven data analytics continuum for every stage of integrated circuit (IC) chip development.
The Synopsys EDA Data Analytics solution is the first of its kind in the semiconductor industry to provide AI-driven insight and optimization to drive improvements across exploration, design, manufacturing, and testing processes. The solution combines the latest advances in AI to curate and operationalize magnitudes of heterogenous, multi-domain data to accelerate root-cause analysis and achieve greater design productivity, manufacturing efficiency, and test quality.
From the news: The AI-driven Synopsys EDA Data Analytics (.da) solution includes:
Synopsys Design.da to perform deep analysis of data from Synopsys.ai design execution, providing chip designers with comprehensive visibility and actionable design insights to uncover power, performance, and area (PPA) opportunities.
Synopsys Fab.da to store and analyze large streams of fab equipment process control data that increase operational efficiencies and maximize product quality and fab yield.
Synopsys Silicon.da to collect petabytes of silicon monitor, diagnostic, and production test data from test equipment to improve chip production metrics, such as quality, yield, and throughput and silicon operation metrics, such as chip power and performance.
From the news: “As IC complexity grows and market windows shrink, the semiconductor industry is increasingly adopting artificial intelligence technologies to enhance the quality of results (QoR), speed verification and testing, improve fab yield, and boost productivity across multiple domains spanning the entire IC design flow,” said Sanjay Bali, Vice President of Strategy and Product Management for the EDA Group at Synopsys. “With the new data analytics capabilities within the Synopsys.ai EDA suite, companies can now aggregate and leverage data across every layer of the EDA stack from architecture exploration, design, test, and manufacturing to drive improvements in PPA, yield, and engineering productivity.”
Discussing this, allaboutcircuits.com said, “Synopsys aims to keep pace with this accelerating field by unveiling a new extension to its Synopsys.ai EDA suite. This announcement follows the release of Google’s (NASDAQ: GOOG) DeepMind, which uses AI to accelerate its in-house chip designs. Both of these announcements indicate how advanced machine learning algorithms are shaping IC development and how they might be used as a tool for designers in such fields.”
Cadence Design Systems, Inc. (Nasdaq: CDNS), describing its innovation in AI says, “The Cadence Joint Enterprise Data and AI (JedAI) Platform is able to harness this rich lode of EDA data in an open, artificial intelligence (AI)-driven, large-scale data analytics environment, allowing engineering teams to visualize the data, uncover hidden data trends, and automatically generate design improvement strategies leading to improved design performance and engineering productivity.”
“With the Cadence JedAI Platform, Cadence unifies its computational software innovations in data and AI across Verisium AI-Driven Verification, Cadence Cerebrus Intelligent Chip Explorer’s AI-driven implementation, and Optimality Intelligent System Explorer’s AI-driven system analysis, enabling a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to leveraging big data and AI to optimize multiple runs of multiple engines across an entire SoC design and verification flow.”
Electronic Design recently reported, “Skilled engineers remain the driving force for innovation in chips. But it’s no secret that electronic design automation (EDA) companies are folding AI into more of their offerings to speed up design and verification.”
“But as industry insiders tell it, these AI-powered EDA tools don’t have enough intelligence to actually replace human designers anytime soon. Instead, the biggest difference these tools are having is on the productivity front, with AI reducing the number of hours that engineers spend on the more tedious phases of the design and verification process,” said Amit Gupta, VP and GM of Siemens Digital Industries Software’s custom IC verification division.”
“Specifically, three main types of AI are becoming prevalent in the world of EDA. The most mature are what he calls “adaptive AI,” which enhances existing EDA processes to cut down on manual labor, and “additive AI,” which learns over time to save engineers from repetitive work. Further along on the roadmap is “assistive” AI. It can pinpoint weak points that can negatively impact the chip design’s performance and then figure out the root cause.”
For investors following the sector, the AI implementation for EDA is still evolving and the next chapter will represent untapped potential for those willing to bet on the revolution.
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