GBT Technologies Inc. ( OTC PINK: GTCH ) (“GBT” or the “Company”), nonprovisional patent application for automatic correction of Integrated Circuits electrical connectivity mismatches, received a notice of allowance from the United States Patent and Trademark Office (“USPTO”). The application was filed on August 3, 2022 and received application #17880055. The non-provisional patent application describes programmatic algorithms to automate integrated circuits electrical connectivity mismatches correction with the goal of achieving faster and more efficient designs, particularly for advanced nanometer range of 5nm and below. A Layout-Vs-Schematics (“LVS”) Verification program is an integral part of the integrated circuits (“IC”) signoff process to compare the electrical connectivity (wiring) of an IC layout against its schematic diagram. If a connectivity mismatch is detected that means a faulty wiring connection exists between electronic components and may lead to a non-functional chip’s circuit or wrong electrical outcome. Typically, in a custom and semi-custom Analog, MIXED and RF layout styles, these corrections must be fixed manually which takes a significant amount of design time and may have further impacts resulting in other geometrical design rules violations and similar. GBT’s non-provisional patent application seeks to protect an algorithmic system and method to perform an automatic LVS correction with a click of a button. The system will read the IC’s schematic and layout data, compare their electrical connections (wiring) and in case of mismatches, disconnect the incorrect wires, and re-route them in the correct way.
